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HD74ALVCH16831
1-to 4 Address Register / Driver with 3-state Outputs
REJ03D0031-0200Z (Previous ADE-205-194(Z)) Rev. 2.00 Oct.02.2003
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The s (SEL) HD74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select ( input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output enable (OE) controls. Each OE controls two groups of nine outputs. When SEL is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic state (high or low logic level). When OE is logic high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. SEL and OE do not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
* * * * * VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
Rev.2.00, Oct.02.2003, page 1 of 11
HD74ALVCH16831
Function Table
Inputs OE H L L L L SEL X H H L L CLK X X X A X L H L H Z L H L H Output Y
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition
Rev.2.00, Oct.02.2003, page 2 of 11
HD74ALVCH16831
Pin Arrangement
4Y1 3Y1 GND 2Y1 1Y1 VCC NC A1 GND NC A2 GND NC A3 VCC NC A4 GND CLK OE1 OE2 SEL GND A5 A6 VCC A7 NC GND A8 NC GND A9 NC VCC 4Y9 3Y9 GND 2Y9 1Y9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
1Y2 2Y2 GND 3Y2 4Y2 VCC 1Y3 2Y3 GND 3Y3 4Y3 GND 1Y4 2Y4 VCC 3Y4 4Y4 GND 1Y5 2Y5 3Y5 4Y5 GND 1Y6 2Y6 VCC 3Y6 4Y6 GND 1Y7 2Y7 GND 3Y7 4Y7 VCC 1Y8 2Y8 GND 3Y8 4Y8
(Top view)
Rev.2.00, Oct.02.2003, page 3 of 11
HD74ALVCH16831
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage
*1, 2
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
Unit V V V mA mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation *3 at Ta = 55C (in still air) Storage temperature Notes:
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TVSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO IOH Min 2.3 0 0 -- -- -- Low level output current IOL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -12 -12 -24 12 12 24 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.2.00, Oct.02.2003, page 4 of 11
HD74ALVCH16831
Logic diagram
OE1 OE2 CLK A1
20 5 21 19 8 4
1Y1 2Y1 3Y1 4Y1
CLK
2
D
Q
1
SEL
22
To eight other channels ht
Rev.2.00, Oct.02.2003, page 5 of 11
HD74ALVCH16831
Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) Min Max -- -- 0.7 0.8 V IOH = -100 A IOH = -6 mA, VIH = 1.7 V IOH = -12 mA, VIH = 1.7 V IOH = -12 mA, VIH = 2.0 V IOH = -12 mA, VIH = 2.0 V IOH = -24 mA, VIH = 2.0 V IOL = 100 A IOL = 6 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.8 V IOL = 24 mA, VIL = 0.8 V A VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V *1 A A A VOUT = VCC or GND VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at VCC or GND -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 5 -- -- -- -- 500 10 40 750 Unit Test Conditions V
2.3 to 2.7 1.7 2.7 to 3.6 2.0 2.3 to 2.7 -- 2.7 to 3.6 -- 2.3 2.3 2.7 3.0 3.0 2.0 1.7 2.2 2.4 2.0 -- -- -- -- -- 45 -45 75 -75 -- -- --
2.3 to 3.6 VCC-0.2 --
VOL
2.3 to 3.6 -- 2.3 2.3 2.7 3.0
Input current
IIN IIN (hold)
3.6 2.3 2.3 3.0 3.0 3.6
Off state output current
IOZ ICC
3.6 3.6
Quiescent supply current ICC
3.0 to 3.6 --
Note:
1. This is the bus hold maximum dynamic current required to switch the input from one state to another.
Rev.2.00, Oct.02.2003, page 6 of 11
HD74ALVCH16831
Switching Characteristics
(Ta = -40 to 85C)
Item Symbol VCC (V) Min Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.5 5.0 7.5 Max -- -- -- 4.0 4.1 3.6 4.5 4.4 3.9 5.2 5.2 4.4 5.1 5.0 4.3 5.5 4.7 4.5 -- -- -- -- -- -- -- -- -- -- -- -- pF pF Control inputs Data inputs ns ns ns ns OE Y ns OE Y SEL Y CLK Y ns A Y Unit MHz FROM (Input) TO (Output)
Maximum clock frequency fmax
2.50.2 150 2.7 150 3.30.3 150
Propagation delay time
tPLH tPHL
2.50.2 1.2 2.7 -- 3.30.3 1.6 2.50.2 1.1 2.7 -- 3.30.3 1.5 2.50.2 1.3 2.7 -- 3.30.3 1.7
Output enable time
tZH tZL
2.50.2 1.1 2.7 -- 3.30.3 1.2
Output disable time
tHZ tLZ
2.50.2 1.4 2.7 -- 3.30.3 1.6
Setup time
tsu
2.50.2 2.0 2.7 2.0 3.30.3 1.6
Hold time
th
2.50.2 0.7 2.7 0.5 3.30.3 1.1
Pulse width
tw
2.50.2 3.3 2.7 3.3 -- -- -- 3.30.3 3.3
Input capacitance Output capacitance
CIN CO
3.3 3.3 3.3
Rev.2.00, Oct.02.2003, page 7 of 11
HD74ALVCH16831
Test Circuit
See under table 500 S1 OPEN GND
*1 CL
500
Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ CL
V, Vcc=2.50.2V Vcc = 2.7V 3.30.3
OPEN GND 2 x VCC 30 pF
OPEN GND 6.0 V 50 pF
Note:
1.
CL includes probe and lig capacitance.
Rev.2.00, Oct.02.2003, page 8 of 11
HD74ALVCH16831 Waveforms - 1
tr 90 % Input 10 % t PLH Vref 90 % Vref 10 % t PHL tf VIH GND
VOH Output Vref Vref VOL
Waveforms - 2
tr 90 % Timing Input 10 % tsu Vref th GND VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND VIH
Rev.2.00, Oct.02.2003, page 9 of 11
HD74ALVCH16831 Waveforms - 3
tf Output Control 90 % Vref 10 % t ZL Vref t ZH Waveform - B Vref t HZ Vref2 10 % t LZ tr 90 % Vref GND VOH1 Waveform - A Vref1 VOL VOH VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1
Vcc=2.50.2 V Vcc = 2.7 V, 3.30.3 V
VIH
VCC
2.7 V
1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH-0.15 V VOH-0.3 V VCC GND 3.0 V GND
Notes:
1.
2. 3. 4.
All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , tr 2.0 ns, tf 2.0 ns. (VCC = 2.50.2 V) PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. (VCC = 2.7 V, 3.30.3 V) Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform - B is for an output with internal conditions such that the output is high except co when disabled by the output control. The output are measured one at a time with one transition per measurement.
Rev.2.00, Oct.02.2003, page 10 of 11
HD74ALVCH16831
Package Dimensions
As of January, 2003
Unit: mm
41
17.0 17.2 Max 80
1 0.40 *0.18 0.05 0.07 M 0.85 Max
40
6.10
1.0 8.10 0.20 0 - 8 0.50 0.1
*0.15 0.05
0.08
0.10 0.05
1.20 Max
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-80DV -- -- 0.27 g
Rev.2.00, Oct.02.2003, page 11 of 11
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